1. Field of the Invention
Embodiments of the invention relate to a method for manufacturing semiconductor devices. More particularly, embodiments of the invention relate to a method for forming a planarized inter-metal insulation film on a metal wiring layer.
This application claims the benefit of Korean Patent Application No. 10-2005-0000377, filed on Jan. 4, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
The various manufacturing processes used to fabricate semiconductor devices include numerous individual processes. Some of the individual processes relate to photolithography, etching, thin film formation, diffusion, planarization, etc. As repeatedly applied in constructive combination to a semiconductor substrate, these processes ultimately form, amongst other potential structures, conductive patterns separated by insulation films.
The planarization of an upper surface of “resulting structure” formed by the layered combination of conductive patterns and insulation films during the overall manufacturing process fabricating a semiconductor device is a very important technical consideration. A properly planarized upper surface is necessary predicate to the accurate and convenient application of subsequent processes adapted to form additional elements, layers, etc. on the resulting structure. Therefore, careful consideration is given to the nature of the materials forming the upper surface of the resulting structure and the processes used to planarize it.
For example, conventional methods of surface planarization use a material having significant fluidity, such as borophosphosilicate glass (BPSG) or spin on glass (SOG). However, even in processes using these beneficial materials, it is difficult to obtain a completely planarized upper surface of the resulting structure. Thus, the conventional methods using highly fluid materials generally include an additional step of heating material to or near its melting point in order to reflow the material or remove solvent(s) contained in the material. Unfortunately, this additional thermal treatment process usually requires the application of high-temperatures which cause collateral problems, such as the short channel effect in active devices formed within the semiconductor device. This being the case, chemical mechanical polishing (CMP) methods are most contemporarily used to planarize the upper surface of semiconductor devices.
Against this processing state, contemporary semiconductor devices are becoming ever more highly integrated. Dense circuit and element integration necessitates the use of a plurality of metal wiring layers separated by inter-metal insulation films. The accurate and effective formation of this common combination of metal layers and inter-metal insulation films is also a very important consideration. This is particularly true for multi-layered metal wiring structure, where an increasing number of metal wiring layers and inter-metal insulation films are used.
FIGS. 1A and 1B are cross-sectional views illustrating one conventional method for planarizing an inter-metal insulation film.
Referring to FIG. 1A, a metal wiring layer 20 having a first thickness (t1) is formed on a semiconductor substrate 10. (Semiconductor substrate 10 may include any reasonable number of stacked conductive patterns (not shown) or related inter-layer insulation films (not shown), but for the sake of clarity only a single combination of these elements are illustrated). An inter-metal insulation film 30 is formed on metal wiring layer 20. Inter-metal insulation film 30 is formed with a stepped, second thickness (t2) irregularly formed on the first thickness (t1) of metal wiring layer 20. At this point, it should be noted that within this written description, the term “on” is used to denote layers, elements, etc., formed directly on another layer element, etc., or on intervening layer(s), element(s), etc.
Referring to FIG. 1B, the removal of an upper portion of the irregularly formed (e.g., stepped) inter-metal insulation film 30 is accomplished using a conventional CMP process, whereby a planarized inter-metal insulation film 30a is formed. Planarized inter-metal insulation film 30a is formed to a third thickness (t3) on metal wiring layer 20.
According to the foregoing conventional method, a significant quantity of material used to form inter-metal insulation film 30 must be removed in order to remove the entire upper portion of the stepped layer. In certain circumstances, the removal of this upper portion of the stepped inter-metal insulation film may result in planarization to an undesirable depth. Additionally, a CMP process sufficient to remove the significant quantity of insulating material is often overly time consuming. Further, the irregular upper surface of the inter-metal insulation layer to which the CMP process is applied makes it difficult to precisely align and remove a specific thickness of material forming the insulation film. Thus, the CMP process may result in a non-uniform upper surface that varies with semiconductor wafer positioning under the CMP process. Excellent planarization characteristics, therefore, cannot be obtained using the conventional methods.
FIG. 2 is a graph illustrating a thickness distribution for an inter-metal insulation film measured at a variety of positions on a wafer following planarization of the inter-metal insulation film using the conventional method illustrated in FIGS. 1A and 1B.
The data illustrated in FIG. 2 was obtained from samples comprising a metal wiring layer having the structure shown in FIG. 1A and formed to a thickness of about 12,000 Å on a semiconductor substrate. An oxidation film was formed as the inter-metal insulation film. The second thickness of the oxidation film formed on the metal wiring layer is about 32,000 Å and the stepped portion (e.g., the first thickness) of the oxidation film is about 12,000 Å. After the stepped portion of the oxidation film was removed using a conventional CMP process and assuming a target (third) thickness of the oxidation film on the metal wiring layer of about 9,000 Å. Thereafter, a number of measurements were made for the actual thickness of the oxidation film at a variety of positions on the wafer. As can bee seen from FIG. 2, the target (third) thickness of the inter-metal insulation film varied from about 1,500 to 2,000 Å.
In addition to the problems noted above, this test data is exemplary of unacceptable deviations in the actual thickness of the planarized inter-metal insulation layer obtained from use of the conventional methods. Such deviations are particularly apparent between insulation films formed on different wafers and on wafers contained in different processing lots.